The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, includes so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes, and in particular the gate length, of field effect transistors has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues.
In SOI fabrication techniques, devices usually are fabricated in a thin silicon film, and a buried oxide layer (BOX) is disposed between the device and the substrate to separate them. Compared to traditional bulk silicon, SOI technology has many advantages, such as reduced parasitic capacitance, which leads to higher speed and less power consumption, full dielectric isolation of the SOI CMOS device, which eliminates the occurrence of bulk-silicon CMOS device parasitic latch-up effects and makes SOI devices have superior performances including high integration density and good anti-irradiation properties.
In bulk silicon MOSFETs, the bottom of the bulk silicon can be connected to a fixed potential. However, in an SOI MOSFET, the body is electrically isolated from the bottom of the substrate. This “floating body” effect result in drain current “kink” effect, abnormal threshold slope, low drain breakdown voltage, drain current transients, and noise overshoot. The “kink” effect originates from impact ionization. When an SOI MOSFET is operated at a large drain-to-source voltage, channel electrons cause impact ionization near the drain end of the channel. Holes build up in the body of the device, raising body potential and thereby raising threshold voltage. This increases the MOSFET current causing a “kink” in the current vs. voltage (I-V) curves.
In order to resolve the undesirable effects caused by this floating body configuration of conventional SOI MOS, a method of body contacting is usually adopted to connect the “body” to a fixed electric potential such as the source region or the ground. Referring to FIGS. 1 and 2, in the traditional T-type gate structure body-contact, the P+ implantation region formed in one side of the T-type gate is contacted to the P-type body region. During the operation of the MOS devices, the carriers accumulated in the body region are released via flowing through the P+ channel to reduce electric potential of the body region. However, there are still some disadvantages of this T-type configuration such as a complex manufacturing process, an increased parasitic effect, degraded electric properties, and increased device area.
Accordingly, it is desirable to provide improved SOI integrated circuits and methods for fabricating the same that do not suffer from reduced threshold voltages or leakage currents. Moreover, it is desirable to provide SOI integrated circuits and methods for fabricating the same that are simple to manufacture and occupy a relative small area on the SOI substrate. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description of the disclosure and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.